Field effect transistors generally have a source electrode, a drain electrode and a gate electrode, which controls the current between the source electrode and the drain electrode. A reduced electric field on the current controlling gate electrode is desirable to make the threshold voltage more stable and to improve the reliability of the gate structure. In the prior art, field-plates have been used for this purpose.
U.S. Pat. No. 8,530,978, issued Sep. 10, 2013, U.S. Pat. No. 8,853,709, issued Oct. 7, 2014, U.S. Pat. No. 8,941,118, issued Jan. 27, 2015, and U.S. patent application Ser. No. 14/290,029, filed May 29, 2014, which are incorporated herein by reference, describe field effect transistors, which are GaN FETs that have normally-off operation, high voltage operation, low on-resistance, and desirable dynamic characteristics. However, the prior art normally-off GaN transistor gate structures often experience a drift of threshold voltage under large drain bias.
FIGS. 1A, 1B and 1C show an example of threshold voltage drift for a prior art FET with field plates. FIG. 1A shows the FET threshold voltage before stress, which shows the threshold voltage to be approximately Vg=0 volts. FIG. 1B shows a high 300 volt stress applied to the drain for 150 hours. FIG. 1C shows that after the high voltage stress, the threshold voltage shifted by 0.5 volts to approximately Vg=−0.5 volts. The threshold voltage shift is undesirable.
What is needed are more reliable normally-off high-voltage III-Nitride power transistors, which have reduced or no threshold voltage drift under a large drain bias. The embodiments of the present disclosure answer these and other needs.